Proceedings of the International Display Workshops Volume 31 (IDW '24)
Dec 4 - Dec 6, 2024Sapporo Convention Center
Proceedings of the International Display Workshops Volume 31 (IDW '24)
Dec 4 - Dec 6, 2024Sapporo Convention Center
[AMDp2-6]Bias Stress Reliability of ALD InGaZnO TFTs With HfOx
*Ziheng Bai1, Chunyu Zhang1, Nannan You1, Haitao Zhou1, Jiayi Wang1, Di Geng1(1. Institute of Microelectronics of Chinese Academy of Sciences (China))
Keywords:
InGaZnO,TFT,Bias stress
In this work, the DC bias stress of ALD InGaZnO TFTs is presented (9 nm HfOx + 6 nm IGZO). The Vth shift in NBS up to over-drive gate voltage (Vov) of -4 V is no more than 10 mV. In PBS at Vov ≦ +3 V, the Vth shift is correlated with the power-law formula. When Vov ≦ +3 V (3.3 MV/cm), charge trapping mechanism predominates. The Vov used in 9 nm HfOx + 6 nm InGaZnO at room temperature is recommended in range of -4 V ~ +3 V. Moreover, annealing in 400 Celsius may increase the reliability.