[A-5-03]Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
〇Assawer - Soussou1, Tom - Schram2, Kenichi - Miyaguchi2, Ivan - Chakarov3, Bertrand - Parvais2, Joseph - Ervin3(1. COVENTOR(France), 2. IMEC(Belgium), 3. COVENTOR (US)(United States of America))
