[A-7-02]A Self-Bias NAND Gate and its Application to Non-Overlapping Clock Generator for Extremely Low-Voltage CMOS LSIs
〇Hikaru Sebe1, Kaori Matsumoto2, Ryo Matsuzuka1, Osamu Maida1, Daisuke Kanemoto1, Tetsuya Hirose1(1. Osaka Univ.(Japan), 2. Kobe Univ.(Japan))
