[B-2-4]New Criteria for Suppressing Extrinsic Defect Generation in Ultra Thin SiON Gate Insulator (EOT<1.4nm) for Advanced CMOSFETs
S. Shimamoto1、H. Kawashima2、T. Kikuchi1、Y. Yamaguchi2、A. Hiraiwa2(1.Hitachi, Ltd.(Japan)、2.Renesas Tech. Corp.(Japan))
