[ThD1] Heterogeneous Integration on Silicon Photonics (I)

10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)

[ThD1-02] Scalable Photonic Tensor Processor Based on a Membrane Directly Modulated WDM Laser Array

〇Taishi Sumiya¹, Hidetaka Nishi¹, Nikolaos-Panteleimon Diamantopoulos¹, Mitsumasa Nakajima¹, Takuro Fujii¹, Toshikazu Hashimoto¹, Hiroki Sugiyama¹, Takasumi Tanabe^1,2, Tomonari Sato¹, Shinji Matsuo¹ (1. Device Technology Labs., NTT, Inc. (Japan), 2. Keio Univ. (Japan))

Optical tensor processors using WDM/TDM/SDM multiplexing promise high-throughput AI acceleration, and incoherent (intensity-domain) computation eases chiplet scaling by avoiding inter-chiplet phase alignment. Under limited wavelength budgets, we previously proposed an AWG-based receiver that reuses a fixed WDM wavelength set across transmitter chiplets, but the transmitter relied on discrete light sources, leaving low energy consumption and highly integrated implementation as key challenges. Here we employ an InP/Si membrane directly-modulated-laser (DML) array as a transmitter chiplet, providing multi-wavelength carriers and low-energy input-matrix encoding. Combined with an AWG-router/photodiode receiver PIC, we validate wavelength demultiplexing/routing-enabled multiply-and-accumulate (MAC) functions required for two-axis contraction. As a first step, we demonstrate second-order matrix multiplication using a 6-channel C-band membrane DML array (2.5 mA lasing threshold, 23 GHz 3-dB bandwidth) and a Si receiver integrating an 8×8 SiN AWG and eight Ge photodiodes, enabling wavelength-demultiplexed detection up to 31 Gbaud. MNIST digit recognition with a 100-node single-layer network shows only slight accuracy degradation up to 31 Gbaud. With electrical power consumption of membrane DML estimated at 14 mW per wavelength, the full L=M=N=6 setup is estimated at 37 fJ per operation and 14 TOPS throughput.