[C-12] 集積回路

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[C-12-02] Evaluation of Triple Modular Redundancy Flip-Flop Structures with Reduced Area Delay Power Product in a 22 nm Bulk Process

〇Shuhei Mandai¹, Ryuichi Nakajima¹, Jun Furuta², Kazutoshi Kobayashi¹ (1. Kyoto Institute of Technology, 2. Okayama Prefectural University)

Keywords:

Soft Errors,Flip-Flop

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