General Conference of the Institute of Electronics, Information and Communication Engineers
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Presentation Information

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[D-18-04]FPGA Implementation of Ternary {1,0,-1} Matrix Multiplication + Ternarizer for Edge Learning with TGBNN

〇Masahiro Hayashi1, Riku Ando1, Takayuki Kawahara1 (1. Tokyo University of Science)

Keywords:

edge AI,TGBNN,systolic array

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