[BCS-1] 4th International Workshop on Global Research Initiative for Wireless Technology (4th IGROW)

9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)Candidate for Academic Incentive AwardCareer Explorer

[BCS-1-03] A High-Efficiency Decoupling Power Layout with Reduced Wiring in SOI CMOS Process

◎△Shuto Nakata¹, Satoshi Tanaka¹, Minoru Fujishima¹ (1. Hiroshima Univ.)

Keywords:

SOI CMOS,Power Panel,Power wiring