General Conference of the Institute of Electronics, Information and Communication Engineers
Advanced Search

Presentation Information

10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[D-18-07]CPU Architecture Classification for Partial Binary Code

Keito Kano1, 〇Makoto Takita1, Tomoki Shoji1, Hiroki Kuzuno1, Shohei Kakei2, Yoshiaki Shiraishi1 (1. Kobe University, 2. Nagoya Institute of Technology)

Keywords:

CPU architecture classification,Binary analysis,Machine learning

Back to Session information