Presentation Information

9:00 AM - 10:30 AM JST(12:00 AM - 1:30 AM UTC)

[TPO-1-42]Memory Access Optimization for Super Scaler/VLIW Processors

〇Ren Honma¹, Ryosuke Hosokawa¹, Ryoya Hirota¹, Seiichiro Hiratsuka¹, Akitoshi Matsuda¹ (1. Nishinippon Institute of Technology)

VLIW architecture,Instruction-level parallelism,Parallel memory access,Data memory architecture,Performance evaluation