[17p-C31-1~20] 12.7 Biomedical Engineering and Biochips

3:15 PM - 3:30 PM JST(6:15 AM - 6:30 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation AwardEnglish Presentation

[17p-C31-9] Modeling and Evaluation of a Power Management System for RISC-V-Based Digital Platforms

〇(D)Panithan Srisinsuphya¹, Yasufumi Yokoshiki², Takashi Tokuda¹ (1.Tokyo Inst. of Tech., 2.Aoyama Gakuin Univ.)

Keywords:

IoT,PMU

As digital platforms advance in complexity, the need for sophisticated power management units (PMUs) becomes important. This paper presents a PMU design tailored for RISC-V digital platforms, emphasizing power efficiency through power gating and sequential module activation. By powering only necessary modules and staggering activation, the PMU minimizes power consumption without compromising performance. The system initiates power from the sensor and ADC units, progresses to the RISC-V CPU for data processing, and subsequently records data in external memory, ensuring inactive modules are powered down. Experimental results demonstrate successful power gating and the design of the PMU layout measures 110 × 110 μm.