Presentation Information
[11a-PA1-10]A 0.5-V Lateral-Inhibition STDP Circuit for Low-Power Spiking Neural Networks
〇Kai Sakuma1, Daiki Sato1, Yasufumi Yokoshiki1 (1.Aoyama Gakuin Univ.)
Keywords:
STDP,Spiking Neural Network,Intermittent Driven Circuit
We propose a 0.5-V Lateral-Inhibition STDP Circuit for Low-Power Spiking Neural Networks, targeting memoryless spiking neural networks (SNNs) that do not require pre-training. To accommodate the fixed spike timing interval that occurs during self-learning, a buffer circuit is introduced to linearly compensate the learning rate in the region where Δt ≤ 1.0 μs. In addition, to improve the efficiency of weight increase during the initial learning phase, a constant weight update characteristic is adopted for Δt ≤ 0 μs. Simulation results confirm the weight update behavior with the proposed characteristics.