[4] Advanced Logic and Memory Devices

2:15 PM - 2:35 PM JST(5:15 AM - 5:35 AM UTC)

[4-03] Below 10A CMOS- Double CFETs with Dielectric-wall-stress by Isolation-last Process for 0.0069 um² of SRAM-cell Design

*Yi-Sung Chen², Yu-Shang Shih², Hao-Ming Huang², Ting-Kuan Ma², E Ray Hsieh¹ (1. National Yang Ming Chiao Tung University (Taiwan), 2. National Central University (Taiwan))