[A-19] ハードウェアセキュリティ

12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)Candidate for Academic Incentive Award

[A-19-08] On Efficient Security Analysis for Logic Locking Implementation in Approximate Circuits

◎Yuto Takino¹, Yusaku Harada¹, Daiki Miyahara¹, Yang Li¹, Yuko Hara², Kazuo Sakiyama¹ (1. The University of Electro-Communications, 2. Tokyo Institute of Technology)

Keywords:

Logic Locking,Approximate Computing,IP Protection,Integrated Circuit