[C-12] 集積回路

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[C-12-18] Design of D flip-flop with extremely low-voltage NAND gates

◎△Shintaro Sumi¹, Hikaru Sebe¹, Daisuke Kanemoto¹, Tetsuya Hirose¹ (1. Osaka Univ.)

Keywords:

Extremely low voltage,Logic gates,Flip flop,Energy harvesting