Presentation Information
[A-14-25]FPGA-Oriented Power Evaluation of an MVDR Beamformer
〇Renjinxian Zou1, Ken Takaki1, Yoshihiro Kawahara1 (1. The University of Tokyo)
Keywords:
FPGA,MVDR beamforming,Low power consumption,Signal to Distortion Ratio
Microphone-array beamforming is important for wearable real-time hearing aid systems, which require high-quality audio processing under strict battery constraints. A traditional beamformer, MVDR (Minimum Variance Distortionless Response), suppresses interference while maintaining a distortionless response in the target direction. FPGA (field-programmable gate array) implementations provide compact and portable signal-processing units suitable for real-time applications; however, the complex-valued matrix operations required by MVDR consume substantial power. This work evaluates how the numerical precision of the beamforming weights, intermediate solution vector, and covariance-matrix elements affects the trade-off between power consumption and SDR (Signal-to-Distortion Ratio). Evaluation signals are generated in MATLAB, we access the fixed-point FPGA implementation through RTL (Register-Transfer Level) simulation and post-synthesis on-chip power estimation in Vivado. The selected bit widths reduce the estimated total on-chip power from 7.374W to 2.505W, while the SDR decreases from 21.51dB to 19.52dB.