[A-9] Wide Band Systems

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)Candidate for Academic Incentive Award

[A-9-10] Improvement of BER Performance in 1-Bit ADC Reception via LLR Design Using Log-Sum-Exp Method

◎Kenshin Tagaya¹, Masato Saito¹, Takaya Yamazato² (1. University of the Ryukyus, 2. Nagoya Univ.)

Keywords:

1-bit ADC,Stochastic Resonance,Set Partitioning,Coded Modulation,Low Density Parity Check Code

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