[A-7-1]A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation
H. Koike1, T. Ohsawa1, S. Miura1, H. Honjo1, K. Kinoshita2, S. Ikeda1, T. Hanyu1, H. Ohno1, T. Endoh1(1.Tohoku Univ., 2.NEC Corp. (Japan))
