[A-7-03]Monolithic 3D Hetero-Integrated Circuits with 2D Electronics
〇Jhe-Ting Hong1, Ta Fan1, Cheng-Yang Syu1, Li-Syuan Hao1, Yu-Chen Liu1, Nei-Chih Lin2, Chih-Chao Yang2, Chao-Hui Yeh1,3(1. The Inst. of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. Taiwan Semiconductor Res. Inst. (Taiwan), 3. Department of Electrical Engineering, National Tsing Hua Univ. (Taiwan))
This study presents the integration of two-dimensional (2D) transition metal dichalcogenides (TMDs) with three-dimensional (3D) silicon FinFETs in a monolithic 3D (M3D) CMOS inverter architecture. Addressing the limitations of Moore’s Law, this approach utilizes vertical stacking and heterogeneous integration to enhance device miniaturization and performance. We detail a fabrication process involving an upper-tier n-channel MoS2 transistor on a lower-tier p-channel Si FinFET, demonstrating enhanced device performance through the advantageous properties of 2D materials. This paper successfully demonstrates the feasibility of heterogeneous integration of 3D and 2D technologies.
