[OP-01]Welcome Address
Yasuyuki Miyamoto(Chair, Organizing Committee)
2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
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2024 International Conference on Solid State Devices and Materials
Sep 1 - Sep 4, 2024Arcrea HIMEJI
You can search for presentations in this event.
SearchSearch Results(619)
[OP-02]Welcome Address
Tsunenobu Kimoto(President, The Japan Society of Applied Physics)
[AW]SSDM Award/SSDM Paper Award Ceremony
[PL-01 (Plenary)]Japan's Semiconductor Strategy
〇Hisashi Kanazashi1(1. Ministry of Economy, Trade and Industry)
[PL-02 (Plenary)]Creating the Future of Compute: The Next Chapter of Moore's Law
〇Sanjay Natarajan1(1. Intel Corp.)
[PL-03 (Plenary)]Gallium Oxide Electronics - Power, Harsh Environment, and Something New -
〇Masataka Higashiwaki1(1. Osaka Metropolitan Univ.)
[PL-04 (Plenary)]Evolution of Chiplet packaging architectures advancing AI and HPC growth
〇Daniel Ng1(1. AMD)
[A-1-01 (Invited)]3D stacked devices and MOL innovations for post-Nanosheet CMOS scaling
〇Steven Demuynck1、Victor Vega Gonzalez1、Camila Toledo1、Karen Stiers1、Cassie Sheng1、Andy Peng1、Dmitry Batuk1、Maryam Hosseini1、Anne Vandooren1、Lucas Lima1、Naoto Horiguchi1、Serge Biesemans1(1. imec (Belgium))
[A-1-02]Source-Drain Damage of Monolithic Complementary Field Effect Transistors: A Comprehensive Study of Failure Modes and Mitigation Strategies
〇Camila Toledo de Carvalho Cavalcante1, Steven Demuynck1, Emmanuel Dupuy1, Thomas Chiarella1, BT Chan1, Pallavi Puttarame Gowda1, Il Gyo Koo1, Hans Mertens1, Anne Vandooren1, Farid Sebaai1, Jef Geypen1, Sujith Subramanian1, Lucas Petersen Barbosa Lima1, Serge Biesemans1, Naoto Horiguchi1(1. imec, Leuven, Belgium (Belgium))
[A-1-03]Demonstration of Poly Gate Cut Process at Tight Gate Pitch of 50nm and High Gates Aspect Ratio for Advanced Device Architectures
〇Xiuju Zhou1, Zheng Tao 1, Hans Mertens1, Emmanuel Dupuy1, Anabela Veloso1, Boon Teik Chan1, Sujith Subramanian1, Naoto Horiguchi1, Serge Biesemans1, Elisabeth Camerotto2, Haseeb Kazi2, Ziad El Otell2(1. IMEC (Belgium), 2. Lam Res. Corp. (United States of America))
[A-1-04]Low-Thermal Budget Activation for 3D Integration by Green Nanosecond Laser
〇Hongxu Liao1, Yandong Ge1, Haixia Li1, Lanyi Xie2, Qing Wang1, Ming Li1,3, Ru Huang1,3(1. School of Integrated Circuits, Peking University (China), 2. Department of Energy and Resources Engineering, Peking University (China), 3. Beijing Advanced Innovation Center for Integrated Circuits (China))
[A-1-05]Transferring Compressive or Tensile Stress from Stressors to Si Layers: A Novel Approach
〇Pablo Acosta Alba1, Mayara Auricchio1, Patrice Gergaud1, Jean-Michel Hartmann1, Shay Reboh1(1. Univ. Grenoble ALpes, CEA-LETI (France))
[A-2-01]On-Wafer Polarity-Specific Response Plasma Charging Recorder
with Fin-Coupling Structure by FinFET Technology
Han-Lin Huang1, 〇Wei Chang1, Yu-Der Chih2, Jonathan Chang2, Chrong-Jung Lin1, Ya-Chin King1(1. National Tsing Hua Univ. (Taiwan), 2. Taiwan Semiconductor Manufac. Company (Taiwan))
[A-2-02]1T EUV/DUV Detector in Fully Compatible 16nm FinFET Logic Process
〇Wei-Hwa Lin1, Ting-Kai Huang2, Yue-Der Chih3, Yih Wang3, Jonathan Chang3, Ya-Chin King1, Chrong Jung Lin1,2(1. Institute of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. College of Semiconductor Research, National Tsing Hua Univ. (Taiwan), 3. Design Technology Platform, Taiwan Semiconductor Manufac. Company (Taiwan))
[A-2-03 (Late News)]Efficient Reverse Current Reduction of GeSn-Based pn Diodes by Surface Passivation of ALD-GeO2 and Al2O3 Stacked Structure
〇Yoshiki Kato1, Mitsuo Sakashita1, Masashi Kurosawa1, Osamu Nakatsuka1,2, Shigehisa Shibayama1(1. Grad. Sch. Eng., Nagoya Univ. (Japan), 2. IMaSS., Nagoya Univ. (Japan))
[A-2-04]High-speed, Low-power, Ultra-scaled1T-pTRNG Array with 10-ns of p-bits Generation, 0.3V of the Reading-voltage, and 400-Mbits of the Throughput
〇P. H. Huang1, S. Y. Huang1, Y.-H. Lin1, K. H. Chang1, T. H. Shen1, R. Y. Lyu1, K. Y. Lee1, E Ray Hsieh Hsieh1(1. National Central University (Taiwan))
[A-2-05]Development of Curved CMOS Image Sensors by Using SOI Layer Transfer
〇Masahide Goto1, Shigeyuki Imura1, Hiroto Sato1(1. NHK Sci. & Tech. Res. Labs. (Japan))
[A-4-01]High Performance (111)-Oriented Extremely-Thin Body Ge-On-Insulator nMOSFETs down to 2.1 nm
〇Xueyang Han1, Chia-Tsong Chen1, Kei Sumita1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1. The University of Tokyo (Japan))
[A-4-02]Electron Transport in Ge(Sn) n-type Metal-Oxide-Semiconductor Field-Effect Transistors at Cryogenic Temperatures
〇Yen-Yang Chen1, Kai-Ying Tien1, Chia-You Liu1, Wei-Hsiang Kao1, Jiun-Yun Li1,2(1. National Taiwan Univ. (Taiwan), 2. Taiwan Semiconductor Res. Inst. (Taiwan))
[A-4-03]Te-based layered materials for Fermi-level Depinning on n-Ge
〇Wen Hsin CHANG1, Shogo HATAYAMA1, Naoya OKADA1, Toshifumi IRISAWA1, Yuta SAITO1,2(1. AIST (Japan), 2. Tohoku Univ. (Japan))
[A-4-04 (Late News)]Low-temperature annealing effect on electrical/structural characteristics for SiO2/GeO2/Ge gate stack
〇Hajime Kuwazuru1, Taisei Aso1, Dong Wang2, Keisuke Yamamoto2(1. IGSES, Kyushu Univ. (Japan), 2. FES, Kyushu Univ. (Japan))
[A-4-05]Determining factors of the Effective Work Function of TiN/TiAlC Metal Gates for Advanced Gate-all-around CMOS Integration
〇Kenzo Manabe1, Kazuya Uejima1, Hiroyuki Ota1, Yukinori Morita1, Toshifumi Irisawa1, Yoshihiro Hayashi1(1. National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[A-4-06]Gate-All-Around Vertical Channel Transistor Based on Self-Aligned in 2 Pitch Process for Future DRAM
〇Seunguk Han1(1. Samsung electronics Co., Ltd. (Korea))
[A-5-01 (Invited)]Gate Stack Engineering of Ferroelectric HfZrO2 from Multi-Level Non-Volatile Memory (NVM) to Analog-based Synapse
〇Min-Hung Lee1, Zhao-Feng Luo1, Kuo-Yu Hsing2, Fu-Shen Chang1, Jia-Yang Lee1, Yii-Tay Chang1, Cheng-Hong Liu1(1. National Taiwan Univ. (Taiwan), 2. National Yang Ming Chiao Tung Univ. (Taiwan))
[A-5-02]Impact of Amorphous TiN Metal-Cap with High Residual Stress on Ferroelectricity of Hf0.5Zr0.5O2 for FeFET Memory with Low Voltage Operation
〇TADASHI YAMAGUCHI1, Shibun Tsuda1, Takahiro Kono1, Yoshiki Yamamoto1, Atsushi Amo1, Kazuyuki Omori1, Seiji Muranaka1, Masao Inoue1(1. Renesas Electronics Corp. (Japan))
[A-5-03]Correlative Behavior between Defect Generation and Ferroelectricity in Hf0.5Zr0.5O2
〇Yukinori Morita1, Hiroyuki Ota1, Shutaro Asanuma1, Shinji Migita1(1. AIST (Japan))
[A-6-01 (Invited)]Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs
〇Hiroshi Oka1, Hidehiro Asai1, Takumi Inaba1, Shunsuke Shitakata1, Hitoshi Yui1, Hiroshi Fuketa1, Shota Iizuka1, Kimihiko Kato1, Takashi Nakayama1, Takahiro Mori1(1. National Institute of Advanced Industrial Science and Technology (AIST) (Japan))
[A-6-02]Comparative Analysis of Cryogenic Threshold Voltage and On-current Variability in 65nm Bulk and FDSOI MOSFETs
〇Zihao Liu1, Tomoko Mizutani1, Kiyoshi Takeuchi1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1(1. The Univ. of Tokyo (Japan), 2. The National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[A-6-03]Accurate Evaluation of Effective Mobility in Si nMOSFETs at Cryogenic Temperature by Introducing Quasi-Static C-V Method
〇Yutong Chen1, Zhao Jin1, Xueyang Han1, Hiroshi Oka2, Takahiro Mori2, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1. The Univ. of Tokyo (Japan), 2. National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[A-6-04]A Correction Method of Split C-V Characteristics in MOSFETs by Using Transmission Line Model for Accurate Extraction of Effective Mobility
〇Zhao Jin1, Yutong Chen1, Xueyang Han1, Hiroshi Oka2, Takahiro Mori2, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1. The Univ. of Tokyo (Japan), 2. National Inst. of Advanced Indus. Sci. and Tech. (Japan))
[A-6-05]Assessment and optimization of the cascaded transistor method for the direct extraction of access resistance components in FinFET and NSFET devices.
〇Pierre Eyben1, An De Keersgieter1, Philippe Matagne1, Hans Mertens1, Thomas Chiarella1, Clément Porret Porret1, Camila Toledo de Carvalho Cavalcante1, Yong Kong Siew1, Jerome Mitard1, Naoto Horiguchi1(1. Imec (Belgium))
[A-7-01 (Invited)]Realization of CMOS Operation in 3-Dimensional Stacked FET with Self-Aligned Direct Backside Contact
〇Juhun Park1, Jaehyun Park1, Jejune Park1, Kyuman Hwang1, Jinchan Yun1, Dahye Kim1, Sungil Park1, Jinwook Yang1, Jae Won Jeong1, Chuljin Yun1, Jinho Bae1, Daihong Huh1, Deukho Yeon1, Sanghyeon Kim1, Seungeun Baek1, Soomin Son1, Junghan Lee1, Tae-sun Kim1, Seungjun Lee1, Sun-Jung Lee1, Sang Wuk Park1, Bong Jin Kuh1, Daewon Ha1, Sangjin Hyun1, Su Jin Ahn1, Jaihyuk Song1(1. Samsung Electronics Co., Ltd. (Korea))
[A-7-02]Comparative Analysis of Middle Dielectric Isolation (MDI) Integration Approaches in Monolithic Complementary Field Effect Transistors: ‘MDI-First vs MDI-Last’
〇Camila Toledo de Carvalho Cavalcante1, Steven Demuynck1, Alfonso Sepulveda Marquez1, Maria Chistiakova1, Subhobroto Choudhury1, Geert Mannaert1, Farid Sebaai1, Maryam Hosseini1, Anne Vandooren1, Pallavi Puttarame Gowda1, Emmanuel Dupuy1, BT Chan1, Hans Mertens1, Jef Geypen1, Sujith Subramanian1, Lucas Petersen Barbosa Lima1, Serge Biesemans1, Naoto Horiguchi1(1. imec, Leuven, Belgium (Belgium))
[A-7-03]Monolithic 3D Hetero-Integrated Circuits with 2D Electronics
〇Jhe-Ting Hong1, Ta Fan1, Cheng-Yang Syu1, Li-Syuan Hao1, Yu-Chen Liu1, Nei-Chih Lin2, Chih-Chao Yang2, Chao-Hui Yeh1,3(1. The Inst. of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. Taiwan Semiconductor Res. Inst. (Taiwan), 3. Department of Electrical Engineering, National Tsing Hua Univ. (Taiwan))
[A-7-04]Withdrawn
[B-1-01 (Invited)]Materials Development and Interfacial Engineering for Emerging Ferroelectric Memories
Geun Hyeong Park1, Se Hyun Kim1, 〇Min Hyuk Park1(1. Seoul National Univ. (Korea))
[B-1-02]Understanding of Imprint Behavior of Ferroelectric Hf0.5Zr0.5O2 thin Film: Role of Charge Injection and Field Cycling
〇Zhenhong Liu1, Zuochen Cai1, Mitsuru Takenaka1, Shinichi Takagi1, Kasidit Toprasertpong1(1. The University of Tokyo (Japan))
[B-1-03]New insight of ferroelectric Hf0.5Zr0.5O2 properties under cryogenic
temperatures in integrated ferroelectric capacitors
〇Flavien Berthaud1, Liam Hosier1, Niccolo Castellani1, Jean Rottner1, Valentina Méli1, Laurent Grenouillet1, Julie Laguerre1, Catherine Carabasse1, Jean Coignus1, Mikaël Cassé1, Simon Martin1(1. Univ. Grenoble Alpes, CEA, Leti F-38000 Grenoble (France))
[B-1-04]Universal Temperature-Strain Phase Diagram of HfxZr1-xO2 Films
Towards to Ferroelectric Phase Engineering
Tianning Cui1, Zhipeng Xue1, Danyang Chen1, Yuyan Chen1, Jingquan Liu1, Mengwei Si1, 〇Xiuyan Li1(1. Shanghai Jiao Tong University (China))
[B-2-01 (Invited)]FeFET Multi-level Cell Programming for In-memory Computation Arrays
Alptekin Vardar1、Marcel Günther1、Franz Müller1、Nellie Laleni1、〇Thomas Kämpfe1(1. Fraunhofer Institute for Photonic Microsystems (Germany))
[B-2-02]1S1R Multi-Level-Cell for Dense Quantized Recurrent Spiking Neural Network Inference Computing
〇Joel Minguet Lopez1, Manon Dampfhoffer2, Gabriele Navarro1, Mathieu Bernard1, Catherine Carabasse1, Niccolo Castellani1, Thomas Magis1, Chiara Sabbione1, Gabriel Molas1, François Andrieu1(1. Univ. Grenoble Alpes, CEA, Leti (France), 2. Univ. Grenoble Alpes, CEA, List (France))
[B-2-03]Analog In-Memory Search Technology Based on Automotive Grade NOR Flash Memory
〇Po Hao Tseng1, Feng-Ming Lee Lee1, Tian-Cig Bo1, Yu-Hsuan Lin1, Chen-Chi Liu1, Ming-Hsiu Lee1, Kuang-Yeu Hsieh1, Keh-Chung Wang1, Chih-Yuan Lu1(1. Macronix International Co., Ltd. (Taiwan))
[B-2-04]A Novel Decrement Program-Verify Scheme of a 2T NOR Flash eNVM-Based In-Memory Computing Technology
〇Yu-Hsuan Lin1, Yu-Yu Lin1, Feng-Min Lee1, Po-Hao Tseng1, Pei-Ying Du1, Chih-Chieh Lin1, Dai-Ying Lee1, Ming-Hsiu Lee1, Kuang-Yeu Hsieh1, Keh-Chung Wang1, Chih-Yuan Lu1(1. Macronix International Co., Ltd. (Taiwan))
[B-3-01 (Invited)]HfO2-based Ferroelectric Capacitors for Non-Volatile Memory:
Going from Single Devices to Memory Arrays
〇Ruben Alcala1, Roberto Guido1, Pramoda Vishnumurthy1, Alfred Kersch2, Thomas Mikolajick1, Uwe Schroeder1(1. NaMLab (Germany), 2. Univ. of Applied Sciences (Germany))
[B-3-02]Unipolar Polarization Switching and High-endurance Operation of HZO/Si Anti-ferroelectric FETs
〇Shin-Yi Min1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1. The Univ. of Tokyo (Japan))
[B-3-03]Enhanced Ferroelectric Field Effect Transistor via Interlayer Engineering Featuring Memory Window of 3.6V, Endurance > 109 cycles, and Multi-Level Storage for NAND Memory
〇Jun Lan1, Haoran Peng1, Wenhui Wang1, Zhixiong Li1, Guobiao Zhang1, Mei Shen1, Xuewei Feng2, Jiamin Li1, Feichi Zhou1, Longyang Lin1, Yida Li1(1. Southern University of Science and Technology (China), 2. Shanghai Jiao Tong University (China))
[B-3-04 (Late News)]BEOL Compatible High-reliability La-doped ZrO2 Antiferroelectric Capacitor
〇Jianguo Li1, Junliang Zhou2, Fan Wu2, ChoongHyun Lee1, Yi Zhao1,2(1. Zhejiang University (China), 2. East China Normal University (China))
[B-4-01]High stability of the ferroelectricity against hydrogen gas in (Al,Sc)N thin films
〇Nana Sun1, Kazuki Okamoto1, Shinnosuke Yasuoka1, Soshun Doko2, Naoko Matsui2, Toshikazu Irisawa2, Koji Tsunekawa2, Hiroshi Funakubo1(1. Tokyo Tech (Japan), 2. Canon ANELVA Corp (Japan))
[B-4-02]Enhanced Ferroelectricity in HfO2/ZrO2 Superlattice Ferroelectric Capacitor with TiO2 Seed Layer at Low-Temperature Annealing Process
〇Dongya Li1,3, Huan Liu1,2,3, Peiyuan Du1, Fei Yu1, Chengji Jin1,3, Xiao Yu1,2,3, Yan Liu1, Yue Hao1, Genquan Han1,3(1. State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, Xidian University (China), 2. Research Center for Intelligent Chips (China), 3. Hangzhou Institute of Technology, Xidian University (China))
[B-4-03]Oxygen Dosage Adjusting in ALD Process for Highly-reliable and Fast Ferroelectric HZO Thin Film with a High Remanent Polarization
〇Yu-Chun Li1, Zi-Ying Huang1, Xiao-Na Zhu1,2, David Wei Zhang1,2, Hong-Liang Lu1,2(1. Fudan Univ. (China), 2. Zhangjiang Fudan Int’l Innovation Center (China))
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