International Conference on Solid State Devices and Materials

This presentation discusses Computing-in-Memory (CIM) circuits for high-precision and high-efficiency analog DNN accelerators. Key challenges include achieving high compute signal-to-noise ratio (CSNR) in analog CIM to support diverse workloads like CNNs and Transformers. We introduce a capacitor-reconfigured CIM macro that dynamically configures between a high-precision bit-serial mode for Transformers and a low-precision bit-parallel mode for CNNs, achieving 818-4094 TOPS/W. An on-the-fly saliency-aware hybrid SRAM CIM is also proposed that allocates analog or digital compute based on the saliency of each input. This allows dynamic accuracy-efficiency tradeoffs.