講演情報
[9p-E219-5]High-Inductance Low-Power QFGMOS-based MOS–C Synthetic Inductor for CMOS Applications
〇(D)Ruchita Gupta1, Bhawna Aggarwal2, Maneesha Gupta1, Dharmendra Kumar Upadhyay1 (1.NSUT, New-Delhi, 2.DU, New-Delhi)
キーワード：
MOS C Technique、Synthetic Inductor、Analog Integrated Circuits
This paper presents a compact QFGMOS-based MOS–C synthetic inductor for low-voltage integrated analog applications. The proposed design employs five QFGMOS PMOS and three QFGMOS NMOS transistors along with a single capacitor, realized in Cadence Virtuoso using 180-nm CMOS technology. Operating at ±0.5 V supply, the circuit achieves a high equivalent inductance of 415.79 μH with effective electronic tunability through control voltage and capacitance variation. The proposed topology exhibits low power consumption of 2.98 μW and demonstrates stable inductive behavior confirmed by a 90° phase shift between voltage and current. The results validate the suitability of the proposed synthetic inductor for compact, low-power, and tunable on-chip analog applications.