講演情報
[C-12-35]A Standard 6T-SRAM-Compatible Compute-in-Memory Macro for Multi-Bit MAC Operation via Stochastic Activation
◎△Chien Chia Ni1, Mahfuzul Islam1 (1. Institute of Science Tokyo)
キーワード：
Compute-in-Memory (CIM)、Stochastic Computing、6T-SRAM、CNN Accelerator
This paper proposes a 6T-SRAM-compatible compute-in-memory (CIM) macro that performs multi-bit multiply-accumulate (MAC) operation using only sense amplifiers (SAs). Unlike analog CIM that requires multi-bit ADCs, or prior stochastic CIM that relies on a custom bit cell, the proposed macro operates on a standard 6T-SRAM array without peripheral modification. A stochastic number generator drives the wordline with a 1-bit activation stream each cycle, causing the bitline differential at the SA to fluctuate around its true mean. The SA fires with a probability that varies smoothly with the underlying MAC value, and averaging SA outputs over L cycles yields a multi-bit MAC estimate without any analog-to-digital conversion. The macro was modeled in a bit-level simulator integrated with PyTorch. LeNet-5 with all MAC layers mapped onto the macro (4-bit weights, 4-bit activations, L=128) was trained end-to-end with the macro model in the forward path and evaluated on MNIST, achieving 98.69% test accuracy and confirming the feasibility of multi-bit MAC operation in standard 6T-SRAM using only built-in sense amplifiers.