2003 International Conference on Solid State Devices and Materials

2003 International Conference on Solid State Devices and Materials

2003年9月16日〜9月18日Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan
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International Conference on Solid State Devices and Materials
2003 International Conference on Solid State Devices and Materials

2003 International Conference on Solid State Devices and Materials

2003年9月16日〜9月18日Keio Plaza Inter-Continental Tokyo (Keio Plaza Hotel), Tokyo, Japan

[A-2-5]Eliminating Threshold Voltage Offset of PMOSFETs in High-Density DRAM

Norikatsu Takaura、Riichiro Takemura、Hideyuki Matsuoka、Ryo Nagai、Satoru Yamada、Hisao Asakura、Shin’ichiro Kimura(1.Central Research Laboratory, Hitachi, Ltd.、2.Advanced Device Development Gr., Elpida Memory, Inc.、3.Information & Control System Division, Computer Systems Quality Assurance Sect, Hitachi, Ltd.)
https://doi.org/10.7567/SSDM.2003.A-2-5
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