[MoA3] III-Vs on Si (I)

3:00 PM - 3:15 PM JST(6:00 AM - 6:15 AM UTC)

[MoA3-03] Improved InP HBT reliability by strain-engineered epitaxy on InPOSi

〇Reynald Alcotte¹, Yves Mols¹, Zhao Xiang Guo¹, Abhitosh Vais¹, Sachin Yadav¹, Michiel De Maeyer², Peter Swekis¹, Cesar Roda Neve³, Bruno Ghyselen³, Uthayasankaran Peralagu¹, Bertrand Parvais¹, Nadine Collaert¹, Robert Langer¹, Bernardette Kunert¹ (1. imec (Belgium), 2. Univ. of Ghent (Belgium), 3. Soitec (France))

High-quality III-V layers can be grown on engineered substrates consisting of an InP seed layer bonded to Si (InPOSi) if the thermal strain between the epitaxial layer and the seed layer is managed at growth temperature. This concept is used to grow an InP heterojunction bipolar transistor (HBT) structure, free of relaxation, and with a defect density of 2×10⁴ cm^-2, 10× lower compared to the same device deposited without compensating the thermal strain. DC characterization of devices fabricated on this strain-balanced stack indicates comparable values for key electrical parameters as compared to devices on bulk InP and, similarly, no device degradation in the reliability measurements.