[MoA3] III-Vs on Si (I)

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

[MoA3-05] Lateral Epitaxy of InP/InGaAs/InP Structures on SOI for FinFETs

〇Xiangquan LIU¹, Ziyang GONG¹, Weizhuo LIU¹, Renqiang ZHU¹, Kei May LAU¹ (1. The Hong Kong Univ. of Sci. and Tech. (Hong Kong))

We performed lateral growth of InP/InGaAs/InP structures on a silicon-on-insulator (SOI) platform using lateral aspect ratio trapping (LART) technique and demonstrated FinFETs. The InGaAs channel layer is unintentionally doped, while the InP region is n-doped at a estimated concentration of 2 × 10¹⁸ cm^-3, supplying electrons to the channel layer. FinFETs exhibited gate modulation, showing a novel strategy for monolithically integrated III-V transistors on SOI.