[MoA4] III-Vs on Si (II)

6:00 PM - 6:15 PM JST(9:00 AM - 9:15 AM UTC)

[MoA4-05] Wafer-Scale Growth of Twin-Free InP Micro-Templates on 2-inch SOI (001) Substrates Using the Lateral ART Method

〇Hiroya Homma¹, Hiroki Sugiyama¹, Tatsurou Hiraki¹, Takuro Fujii¹, Tomonari Sato¹, Shinji Matsuo¹ (1. NTT, Inc. (Japan))

The lateral aspect ratio trapping (ART) method is a promising approach for III–V/Si monolithic integration. In this work, we demonstrate wafer-scale growth of high-quality InP micro-templates (MTs) on 2-inch SOI (001) substrates using lateral ART initiated from {311} facets. To address the limited on-wafer uniformity reported in previous studies, we systematically investigated the dependence of rotational twin domain (RTD) formation on growth conditions, focusing on group-V precursor species and flow rates during the intermediate-temperature growth step and its preflow. RTDs were evaluated by sulfuric acid etching followed by Nomarski microscopy, and statistical analysis was performed across a 3 × 3 shot array on the wafer. We found that the V/III ratio during intermediate-temperature growth and the PH₃ flow rate during preflow are key parameters governing RTD density. By optimizing these parameters, RTD density was uniformly suppressed over the entire wafer, achieving a twin-free yield exceeding 90%. These results provide important guidelines for reproducible, wafer-scale III–V/Si integration and future device applications.