[MoB4] Novel vdW Heterostructures

5:15 PM - 5:30 PM JST(8:15 AM - 8:30 AM UTC)

[MoB4-03] Multi-scale Modeling of Monolayer InSe MOSFETs: From First-principles Carrier Transport to Performance Limits of Double-Gate and GAA Architectures

〇Huan-Ming Zhang¹, Xi-chun Fang¹, Yuh-Renn Wu¹ (1. National Taiwan University (Taiwan))

Monolayer InSe is a stable indirect-bandgap semiconductor with favorable transport properties. First-principles and EPW calculations reveal a large valley separation (~0.73 eV), which suppresses intervalley scattering and enables high mobility even under strong electric fields, making it suitable for high-power devices. Monte Carlo simulations yield a room-temperature mobility of ~105 cm²/Vs and a peak drift velocity of 5.6x10⁶ cm/s at 1x10⁵ V/cm. Device-level simulations were carried out using the TCAD framework DDCC, developed by our laboratory, with an HfO₂ dielectric (EOT=1 nm). A comparison of device architectures reveals that while top- and bottom-gate structures offer limited performance, the double-gate InSe MOSFET (top 300 nm, bottom 750 nm) exhibits the best characteristics, delivering an on-current of 242.55 mA/mm. Furthermore, the gate-all-around (GAA) architecture further improves electrostatic controllability.