[TuC2] GaN Vertical Power Devices

11:00 AM - 11:30 AM JST(2:00 AM - 2:30 AM UTC)

[TuC2-01 Invited] Advances and Integration Strategies for High-k Gate Dielectrics in GaN and SiC Power Devices

〇Andrew T. Binder¹, Jeff Steinfeldt¹, Joseph P. Klesko¹, Peter Dickens¹, Kevin Reilly¹, Robert J. Kaplar¹ (1. Sandia National Labs. (USA))

Reduction of channel resistance is a key pathway to improving performance in GaN and SiC MOSFETs rated at 1700 V and below. In planar SiC MOSFETs, channel resistance can account for 30% or more of the total device resistance at these voltage classes. One effective approach to reduce channel resistance is by increasing the permittivity of the gate dielectric, which enhances oxide capacitance and improves channel inversion. Conventional SiC MOSFETs employ SiO₂ gate dielectrics with a permittivity of 3.9; however, we have recently demonstrated the use of high-k HfO₂ gate dielectrics, with permittivity exceeding 22, in GaN MOSFETs and SiC MOS capacitors. Related efforts by other groups, including Hitachi/ABB, further highlight growing interest in high-k dielectrics for SiC devices. This talk presents recent developments in our high-k gate dielectric process and discusses integration strategies for both GaN and SiC MOSFET process flows. Key challenges associated with the reduced thermal budget of HfO₂ are examined. Finally, we analyze bilayer and laminate gate dielectric approaches, including implications for dielectric reliability and lifetime.