[TuC2] GaN Vertical Power Devices

12:15 PM - 12:30 PM JST(3:15 AM - 3:30 AM UTC)

[TuC2-05] Impact of Sidewall-Gate Structure on Quasi-Saturation in Vertical GaN MOSFETs

〇Ting Ci Li¹, Chih-Kang Chang¹, Jun-Xiang Wang¹, Jian-Jang Huang¹ (1. National Taiwan University (Taiwan))

We investigate quasi-saturation behavior in vertical GaN MOSFETs employing a sidewall-gate structure. Compared with conventional trench-gate devices, the sidewall-gate configuration exhibits drain current roll-off and negative transconductance under high gate bias. Electrical measurements show that the onset of current degradation is weakly dependent on drain bias, indicating that the phenomenon is not dominated by drain-induced effects. TCAD simulations reveal that removal of the outer p-GaN enables lateral carrier accumulation along the n-drift/oxide interface, leading to space-charge modulation and localized electric-field crowding. The resulting carrier heating and mobility degradation suppress vertical current injection, resulting in quasi-saturation. These results demonstrate that outer p-GaN plays a critical role in current-path confinement, and that appropriate gate and p-GaN structure engineering is essential for mitigating field-induced current degradation in vertical GaN power devices.