[TuP3A] Epitaxy and process

[TuP3A-01] Self-aligned InGaAs FinFETs on Insulator by Lateral Epitaxy

〇Ziyang Gong¹, Weizhuo Liu¹, Xiangquan Liu¹, Renqiang Zhu¹, Kei May Lau¹ (1. The Hong Kong Univ. of Sci. and Tech. (Hong Kong))

III-V semiconductors such as InP, GaAs and related materials are widely used in high-speed electronic devices, while integration of III-V semiconductor devices on SOI are mostly achieved by wafer bonding, limited by the yield, small wafers and high-cost III-V substrates. Here we report a novel scheme of InGaAs FinFET on SOI realized by lateral aspect ratio trap (LART) technique using MOCVD, featuring lateral epitaxy and self-aligned fin formation process. The unintentionally-doped-InGaAs and n-InP layers are horizontally stacked by the unique lateral epitaxy of the LART scheme. The widths of InGaAs and InP turn into fin widths and spacings between fins after the selective etch of InP. This self-aligned formation of narrow fins and spacings is well controlled by epitaxy thickness, and can easily reach nanometer-level and beyond limitation of resolution of photolithography. The demonstrated FinFET shows a positive threshold voltage of 0.5V resulted from improved gate control than planar devices. The on-off ratio , large subthreshold voltage and low channel mobility indicates further work for improvement.