[TuP3C] Power Devices

[TuP3C-01] Improvement of SiC MOSFETs body diode Qrr up to 30% through semiconductor substrate engineering

〇Eric GUIOT GUIOT¹, Frédéric Allibert¹, Walter Schwarzenbach¹ (1. SOITEC (France))

Soitec’s SmartSiC engineered substrates optimize SiC MOSFET performance by mitigating temperature-dependent body diode reverse recovery charge (Qrr). While traditional Qrr reduction techniques (such as recombination center introduction) typically inflate forward voltage (Vf) and degrade third-quadrant conduction, SiC engineered substrate bypasses this trade-off through an ultra-low resistivity (below 5 mOhm·cm) poly-SiC handle wafer. This architecture yields typically a 10-20 percents reduction in RDSon for 1200V SiC MOSFETs and a decrease in high-temperature reverse recovery energy while maintaining a lowered Vf. Consequently, temperature-induced Eon drift will be reduced by up to 30 percents, ensuring superior switching stability and lower total losses across both first and third quadrants.