[TuP3C] Power Devices

[TuP3C-05] Enhanced Gate Reliability and Low Leakage in p-GaN MOS-Gate HEMTs Using Sputter-Deposited SiO₂ Gate Dielectric

〇Jiun Oh¹, Minji Kim¹, Joon Seop Kwak¹ (1. Korea Inst. of Energy Tech. (Korea))

This work reports the systematic fabrication and electro-thermal characterization of normally-off p-GaN MOS-gate AlGaN/GaN High Electron Mobility Transistors (HEMTs) incorporating a 12 nm sputter-deposited SiO₂ gate dielectric. By strategically integrating the MOS-gate architecture, we achieved a stable positive threshold voltage (Vth) of 1.15 V and a profound reduction in gate leakage current by approximately four orders of magnitude compared to conventional metal-semiconductor (MS) gate references. The proposed MOS-HEMT demonstrated a robust gate breakdown voltage of 10.55 V, significantly extending the gate operating swing margin. Despite a relatively long channel design (Lg = 5μm), the device yielded a peak transconductance of 141 mS/mm and a maximum drain current density of 50 mA/mm at VGS = 6V. These results underscore the efficacy of sputtered SiO₂ in passivating surface states and mitigating hole injection, positioning it as a promising dielectric solution for high-reliability GaN on Si power switching applications.