[C-12] 集積回路

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[C-12-31] A Nonlinearity Compensation Technique for Digital-to-Time Converter in All-Digital PLLs

○ZEZHENG LIU¹, Hongye Huang¹, Yuncheng Zhang¹, Atsushi SHIRANE¹, Kenichi Okada¹　  (1. Tokyo Institute of Technology)

Keywords:

PLL,DTC nonlinearity,frequency synthesizer,fractional-n spur,pre-distortion