Session Details
[C-12]集積回路
Fri. Mar 8, 2024 9:15 AM - 12:15 PM JST
Fri. Mar 8, 2024 12:15 AM - 3:15 AM UTC
Fri. Mar 8, 2024 12:15 AM - 3:15 AM UTC
School of Engineering 104(HIROSHIMA UNIVERSITY Higashi-Hiroshima campus)
Chair:YOSHIKI SASAKI, Saito Ken
[C-12-24]NOTゲートを使用した低電源電圧積分器の設計
○Yorihide Nitta1, Daisuke Mizushima1, Norio Tsuda1, Keishiro Goshima1 (1. Aichi Institute of Technology)
[C-12-25]Operational amplifier Transient analysis simulation in C++ using the modified nodal analysis
Haruma Nakato1, ○Shunji Nakata1 (1. Kindai Univ.)
[C-12-26]Low-Power Optical Modulator Driver Using an Open-Collector ft-Doubler Output Stage
○Keisuke Kawahara1, Toshihiko Baba1 (1. Yokohama National University)
[C-12-27]A Study of optimization for VCO gain and CP current of Fractional-N PLL
○Isamu Mizuno1, Reo Nagasue1, Takefumi Yoshikawa1 (1. Toyama Prefectural University)
[C-12-28]A Compact Class-F LC Oscillator with Multi-resonance Mode for Low Jitter PLL Designs
○Yuang Xiong1, Dingxin Xu1, Yuncheng Zhang1, Atsushi Shirane1, Kenichi Okada1 (1. Tokyo Institute of Technology)
Break time
[C-12-29]A Multi-Phase Frequency Synthesizer with Injection-Locking Ring Oscillator
○Daxu Zhang1, Yuncheng Zhang1, Hongye Huang1, Dingxin Xu1, Atsushi Shirane1, Kenichi Okada1 (1. Tokyo Institute of Technology)
[C-12-30]A Comparator-based Gain Boosted PD Design for 32kHz Reference Oversampling PLL
○Wenqian Wang1, Junjun Qiu1, Atsushi Shirane1, Kenichi OKADA1 (1. Tokyo Institute of Technology)
[C-12-31]A Nonlinearity Compensation Technique for Digital-to-Time Converter in All-Digital PLLs
○ZEZHENG LIU1, Hongye Huang1, Yuncheng Zhang1, Atsushi SHIRANE1, Kenichi Okada1 (1. Tokyo Institute of Technology)
[C-12-32]A Fully Synthesizable DPLL for Spread Spectrum Clock Generation
○Waleed Madany1, Huang Hongye 1, Liu Bangan 1, Shirane Atsushi 1, Okada Kenichi1 (1. Tokyo Institute of Technology)
[C-12-33]Correction of Material Parameters for Electromagnetic Field Analysis in the Design of 100GHz Ultra-CMOS Integrated Circuits
○Yuki Inoue1, Takeshi Yoshida1, Ryo Sakamaki1, Shuhei Amakawa1, Minoru Fujishima1 (1. Hiroshima Univ.)
[C-12-34]A study of 150-GHz CMOS active power divider with cross coupling capacitors
○Leshan Xu1, Satoshi Tanaka1, Takeshi Yoshida1, Minoru Fujishima1 (1. Hiroshima Univ.)