[D-18] ﾘｺﾝﾌｨｷﾞｬﾗﾌﾞﾙｼｽﾃﾑ

12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)

[D-18-13] FPGA Implementation of RISC-V processor using Verilog HDL

○Rikuto Ueta¹, Yukio Mitsuyama¹, Wang Liao¹ (1. Kochi University of Technology)

Keywords:

FPGA,RISC-V