The Institute of Electronics, Information and Communication Engineers General Conference
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Session Details

一般セッションOpen Session : General Session

[D-18]ﾘｺﾝﾌｨｷﾞｬﾗﾌﾞﾙｼｽﾃﾑ

Thu. Mar 7, 2024 9:00 AM - 12:15 PM JST
Thu. Mar 7, 2024 12:00 AM - 3:15 AM UTC
School of Integrated Arts and Sciences　K306(HIROSHIMA UNIVERSITY Higashi-Hiroshima campus)
Chair:Izumi Tomonori, YASUTAKA WADA
9:00 AM - 9:15 AM JST(12:00 AM - 12:15 AM UTC)

[D-18-01]Investigation of a method to accelerate inference processing for edge AI using SoC FPGAs

○Natsuki Tajima1, Nakanishi Chikako1 (1. Osaka Institute of Technology)
9:15 AM - 9:30 AM JST(12:15 AM - 12:30 AM UTC)

[D-18-02]Improvement of transfer method by data partitioning of edge AI and further investigation of acceleration method

○Toshihiro Murai1, Chikako Nakanishi1 (1. Osaka Institute of Technology)
9:30 AM - 9:45 AM JST(12:30 AM - 12:45 AM UTC)

[D-18-03]Investigate data sharing methods for Edge AI using accelerated circuit

○Hiroki Yoshida1, Chikako Nakanishi1 (1. Osaka Institute of Technology)
9:45 AM - 10:00 AM JST(12:45 AM - 1:00 AM UTC)Career Explorer

[D-18-04]Investigation of a speed-up method for "YOLOv7" using shared memory

○Shunsuke Funahashi1, Chikako Nkanishi1 (1. Osaka Institute of Technology)
10:00 AM - 10:15 AM JST(1:00 AM - 1:15 AM UTC)Career Explorer

[D-18-05]How to utilize processing data in the "MoveNet" posture estimation model

○Yasumasa Tanaka1, nakanishi chikako1 (1. Osaka Institute of Technology)
10:15 AM - 10:30 AM JST(1:15 AM - 1:30 AM UTC)

[D-18-06]Model Structure Optimization Software for C++ AI Inference Library

○Kazumi Ihara1, Chikako Nakanishi1 (1. Osaka Institute of Technology)
10:30 AM - 10:45 AM JST(1:30 AM - 1:45 AM UTC)

[D-18-07]Consideration of Circuit Generation Method from Algorithm Description Using HLS IP

○Takahiro Morii1, Murano Koki1 (1. Mitsubishi Electric corporation)
10:45 AM - 11:00 AM JST(1:45 AM - 2:00 AM UTC)

[D-18-08]Circuit Design of FC-NN for Missing Pixel Restoration Model Using Pruning Method

○Jinya Hashiguchi1, Kiyotaka Komoku1, Nobuyuki Itoh1 (1. Okayama Prefectural University)
11:00 AM - 11:15 AM JST(2:00 AM - 2:15 AM UTC)

[D-18-09]Color diffraction circuit for incoherent holography capable of processing 260,000 pixels

○Takayuki Hara1,2, Takashi Kakue2, Tomoyoshi Shimobaba2, Tomoyoshi Ito2 (1. National Institute of Technology (KOSEN), Nagano College, 2. Chiba Univ.)
11:15 AM - 11:30 AM JST(2:15 AM - 2:30 AM UTC)

[D-18-10]A method for accelerating holography computation using LUT-Network

○Riku Inoue1, Yota Yamamoto1, Go Irie1, Yukinobu Taniguchi1 (1. Tokyo University of Science)
11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[D-18-11]Implementation of Image Recognition Applications using APSoC

○Shunsuke Matsumoto1, Yukio Mitsuyama1, Wang Liao1 (1. Kochi University of Technology)
11:45 AM - 12:00 PM JST(2:45 AM - 3:00 AM UTC)

[D-18-12]Error Injection for Soft Error Evaluation on Space Application of SRAM-based FPGA

○Yoshihiro Uemura1, Yukio Mitsuyama1, Wang Liao1 (1. Kochi University of Technology)
12:00 PM - 12:15 PM JST(3:00 AM - 3:15 AM UTC)

[D-18-13]FPGA Implementation of RISC-V processor using Verilog HDL

○Rikuto Ueta1, Yukio Mitsuyama1, Wang Liao1 (1. Kochi University of Technology)
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