General Conference of the Institute of Electronics, Information and Communication Engineers
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Presentation Information

4:30 PM - 5:00 PM JST(7:30 AM - 8:00 AM UTC)

[AI-4-06](from VLSI Symposium 2025) A High-Order Masking with Load-Delay-Equalized WDDL for Provable Side-Channel Security

〇Noriyuki Miura1, Kazuki Monta2, Takuya Wadatsumi2, Jun Shiomi1, Yukihito Hiraga3, Takeshi Sugawara3, Makoto Nagata2 (1. The University of Osaka, 2. Kobe University, 3. The University of Electro-Communications)

Keywords:

Side-Channel Attack Countermeasure,High-Order Masking,WDDL

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