[C-12] Integrated Circuit and Devices

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)Candidate for Academic Incentive Award

[C-12-09] SoC FPGAを用いたカーネルサイズ5×5のConv2D層の高速化手法

◎Rihito Yamamoto¹, Chikako Nakanishi¹ (1. Osaka Institute of Technology Univ.)

Keywords:

edge device,super resolution,faster speed