[C-12] Integrated Circuit and Devices | General Conference of the Institute of Electronics, Information and Communication Engineers

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Session Details

一般セッションC. Electronics Society : C-12．Integrated Circuit and Devices

[C-12]Integrated Circuit and Devices

Tue. Mar 10, 2026 1:45 PM - 5:00 PM JST
Tue. Mar 10, 2026 4:45 AM - 8:00 AM UTC

Building 1 2F S206(Kyushu Sangyo University)

Chair:Kosuge Atsutake(The University of Tokyo), DAISUKE KOBAYASHI(NTT， Inc.)

1:45 PM - 2:00 PM JST(4:45 AM - 5:00 AM UTC)

[C-12-01]高位合成による ASIC 実装を指向した量子ビット方向推定用 DSP の設計

〇Kosei Kurokawa¹, Takashi Imagawa², Kazutoshi Wakabayashi³, Kazutoshi Kobayashi¹ (1. Kyoto Institute of Technology, 2. University of Fukui, 3. The University of Tokyo)

2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)Candidate for Academic Incentive Award

[C-12-02]Design and Evaluation of a Rotated Surface Code Decoder for Quantum Error Correction Using High-Level Synthesis

◎Hiroto Kido¹, Junichiro Kadomoto², Kazutoshi Wakabayashi², Kazutoshi Kobayashi¹ (1. Kyoto Institute of Technology, 2. The University of Tokyo)

2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)Candidate for Academic Incentive AwardCareer Explorer

[C-12-03]A 3D-Stacked Artificial Retinal Chip with CNN-Based Object Recognition

◎△YUQI DUAN¹, Aoi Kataura¹, Akihiro Suzuki¹, Ryotaro Kawasima¹, Kotaro Torazawa¹, Pattaramon Thianmontri¹, Yukino Sakurai¹, Takafumi Fukushima¹, Koji Kiyoyama², Tetsu Tanaka¹ (1. Tohoku University, 2. Nagasaki Institute of Applied Science)

2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)Candidate for Academic Incentive Award

[C-12-04]Fundamental Study on Next-Generation Logic-in-Memory Circuits with Variation Compensation

◎Shu Yamamoto¹, Masanori Natsui¹, Takahiro Hanyu¹ (1. Tohoku Univ.)

2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)Candidate for Academic Incentive Award

[C-12-05]Hierarchical Bit-Line Sensing Scheme for Advanced 3D NAND Flash

◎MAO FONG LUO¹, Toru Tanzawa¹ (1. Graduate School of Infomation, Production and Systems, Waseda University)

3:00 PM - 3:15 PM JST(6:00 AM - 6:15 AM UTC)Candidate for Academic Incentive Award

[C-12-06]Temperature Compensation Design for Multiply-and-Accumulate
Operations in Analog Computing In-Memory

◎GENGYUAN LI¹, Toru Tanzawa¹ (1. Graduate School of Information, Production and Systems, Waseda University)

3:15 PM - 3:30 PM JST(6:15 AM - 6:30 AM UTC)

Break time

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

General Conference of the Institute of Electronics, Information and Communication Engineers

Session Details

[C-12]Integrated Circuit and Devices

[C-12-01]高位合成による ASIC 実装を指向した量子ビット方向推定用 DSP の設計

[C-12-02]Design and Evaluation of a Rotated Surface Code Decoder for Quantum Error Correction Using High-Level Synthesis

[C-12-03]A 3D-Stacked Artificial Retinal Chip with CNN-Based Object Recognition

[C-12-04]Fundamental Study on Next-Generation Logic-in-Memory Circuits with Variation Compensation

[C-12-05]Hierarchical Bit-Line Sensing Scheme for Advanced 3D NAND Flash

[C-12-06]Temperature Compensation Design for Multiply-and-Accumulate
Operations in Analog Computing In-Memory

Break time

[C-12-07]Investigation of YOLOX operation acceleration by edge AI

[C-12-08]Quantization and Accuracy Evaluation of AI Models for SoC FPGA

[C-12-09]SoC FPGAを用いたカーネルサイズ5×5のConv2D層の高速化手法

[C-12-10]ResNetのエッジデバイス上での動作高速化手法の検討

[C-12-11]Proposal of method to reduce the number of circuit activations of ResNet50 using edge AI

[C-12-12]Investigation of Acceleration Methods for MoveNet Using SoC FPGA

Session Details

[C-12]Integrated Circuit and Devices

[C-12-01]高位合成による ASIC 実装を指向した量子ビット方向推定用 DSP の設計

[C-12-02]Design and Evaluation of a Rotated Surface Code Decoder for Quantum Error Correction Using High-Level Synthesis

[C-12-03]A 3D-Stacked Artificial Retinal Chip with CNN-Based Object Recognition

[C-12-04]Fundamental Study on Next-Generation Logic-in-Memory Circuits with Variation Compensation

[C-12-05]Hierarchical Bit-Line Sensing Scheme for Advanced 3D NAND Flash

[C-12-06]Temperature Compensation Design for Multiply-and-AccumulateOperations in Analog Computing In-Memory

Break time

[C-12-07]Investigation of YOLOX operation acceleration by edge AI

[C-12-08]Quantization and Accuracy Evaluation of AI Models for SoC FPGA

[C-12-09]SoC FPGAを用いたカーネルサイズ5×5のConv2D層の高速化手法

[C-12-10]ResNetのエッジデバイス上での動作高速化手法の検討

[C-12-11]Proposal of method to reduce the number of circuit activations of ResNet50 using edge AI

[C-12-12]Investigation of Acceleration Methods for MoveNet Using SoC FPGA

[C-12-06]Temperature Compensation Design for Multiply-and-Accumulate
Operations in Analog Computing In-Memory