[C-12] Integrated Circuit and Devices

4:30 PM - 4:45 PM JST(7:30 AM - 7:45 AM UTC)

[C-12-11] Proposal of method to reduce the number of circuit activations of ResNet50 using edge AI

〇Yuki Tochimori¹, Chikako Nakanishi¹ (1. Osaka Institute Of Technology Univ.)

Keywords:

Edge computing,SoC FPGA,Collaborative Design