Session Details

[D-2]Neuro Computing

Thu. Mar 12, 2026 1:45 PM - 3:45 PM JST
Thu. Mar 12, 2026 4:45 AM - 6:45 AM UTC
Building 2 3F 2E308(Kyushu Sangyo University)
Chair:Ogawa Takehiko(Takushoku University), Satoshi Moriya

[D-2-01]The Development of the 3D SNN Chip for Edge AI Applications

◎△Ryotaro Kawashima1, Aoi Kataura1, Yuqi Duan2, Kotaro Torazawa2, Akihiro Suzuki1, Pattaramon Thianmontri2, Yukino Sakurai3, Takafumi Fukushima1,2, Koji Kiyoyama4, Tetsu Tanaka1,2 (1. Grad. Sch. of Biomedical Engineering, Tohoku Univ., 2. Grad. Sch. of Engineering, Tohoku Univ., 3. Sch. of Engineering, Tohoku Univ., 4. Nagasaki Inst. of Applied Science)

[D-2-02]Study on Reducing Power consumption of All-Spike Analog Brain-Inspired Chip for Deep Neural Networks

〇Kumiko Nomura1, Nishi Yoshifumi1, Minegishi Kazuki1, Takaya Satoshi1 (1. Toshiba Corporation)

[D-2-03]Design of an Energy Harvester for Low-Power Analog Spiking Neural Network Circuits

◎Jiei Hamamoto1, Satoshi Moriya1, Toru Ota1, Hideaki Yamamoto1, Shigeo Sato1 (1. Tohoku Univ.)

[D-2-04]Izhikevichニューロンモデルを利用したスパイキングニューラル ネットワークのジェスチャー認識への応用

◎Qianyu Zhao1, Satoshi Moriya1, Hideaki Yamamoto1, Sato Shigeo1 (1. Tohoku Univ.)

Break time

[D-2-05]四元数ニューラルネットワークによるカラー画像復元

〇Takehiko Ogawa1, Chao Wang1 (1. Takushoku University)

[D-2-06]Optimization of Deep Echo State Networks Using Anti-Hebbian Rule

◎△Taiga Miura1, Ziqiang Li1, Gouhei Tanaka1,2 (1. Nagoya Institute of Technology, 2. The University of Tokyo)

[D-2-07]RVTDSSC for Reducing Parameters and Computational Complexity in NN-DPD

◎Yudai Shiota1, Hiroto Sakaki2, Kenjiro Nishikawa1 (1. Kagoshima Univ., 2. Mitsubishi Electric Corp.)