Presentation Information
[Tu-P-75]Logic Circuit Designs, Processes, and Characterization toward 6-inch 4H-SiC CMOS Platform
*Chihon Saito1, Shunto Higashi1, *Kota Shimizu1, Kosuke Muraoka1, Tatsuya Meguro1, Tomonori Maeda1,2, Hiroshi Sezaki1,2, Akinori Takeyama3, Takeshi Ohshima3, Kazutoshi Kojima4, Yasunori Tanaka4, Shin-Ichiro Kuroki1 (1. RISE, Hiroshima Univ. (Japan), 2. Phenitec Semiconductor Corp. (Japan), 3. QST (Japan), 4. AIST (Japan))