Presentation Information
[P2-4-16]Empirical and Analytical Modelling of Capacitance
Induced Dissipation Losses in Power Semiconductors
*Kaushik Mirdoddi1,3, Roberto Petrella2,3 (1. System-Level Integration Technologies, Power Electronics Division, Silicon Austria Labs GmbH, Villach, Austria (Austria), 2. Power Electronics Division, Silicon Austria Labs GmbH, Villach, Austria (Austria), 3. PEMD Laboratory, Polytechnic Department of Engineering and Architecture, University of Udine, Udine, Italy (Italy))
Keywords:
Characterization,Capacitance losses,Modelling,Sawyer-Tower circuit,Soft-switching