[ED4] Digital and Mixed-Signal Circuits

11:30 AM - 11:45 AM JST(2:30 AM - 2:45 AM UTC)

[ED4-06] Design and Evaluation of Single Flux Quantum Circuits with Josephson Inductors Fabricated by 1 kA/cm² Critical Current Density Process

*Chikai Nakamura¹, Nobuyuki Yoshikawa^1,2,3, Yuki Yamanashi^1,2,3 (1. Yokohama National Univ. (Japan), 2. Institute of Advanced Sciences Yokohama National Univ. (Japan), 3. Institute for Multidisciplinary Sciences, Yokohama National Univ. (Japan))

Keywords:

Josephson junction,SFQ circuit,Josephson inductor

For the large-scale integration of superconducting quantum computers, a promising approach is to use control circuits located on the same temperature stage as the many qubits inside a dilution refrigerator. Since dilution refrigerators have limited cooling power, the control circuits must operate with extremely low power consumption. Single Flux Quantum (SFQ) circuits are well-suited for this purpose, as they can operate at high speed and low power under cryogenic conditions, making them ideal for use as control circuits for superconducting qubits in ultra-low-temperature environments.The bit energy of an SFQ circuit is given by IcΦ₀ [J], where I_C is the critical current of the Josephson junction (JJ) and Φ₀ is the magnetic flux quantum. To minimize power consumption, it is desirable to use a low critical current density (J_C) process, which enables the design of low-power circuits with reduced I_C. However, to maintain circuit functionality, the product LI_C must remain constant in SFQ circuits. Therefore, simply reducing I_C leads to an increase in L, requiring longer superconducting interconnects and resulting in larger circuit area. we reduced the circuit area by replacing superconducting wiring with Josephson Inductors (JI), which utilize JJs as inductors. Circuit fabrication was carried out using the four-layer niobium low-J_C process (J_C = 1 kA/cm²) developed by the National Institute of Advanced Industrial Science and Technology (AIST).We designed and evaluated five types of circuits using JI. Compared to conventional circuits, layout area was reduced by an average of 55%. The bias margin was also comparable to that of conventional designs. Moreover, we found that the delay variation due to I_C fluctuations was suppressed to 1/2 to 1/3 by using JIs.