Presentation Information
[EDP2-01]Miniaturization of a superconductor FPGA utilizing external control reconfiguration
*Sho Matsuoka1, Nobuyuki Yoshikawa1,2,3, Yuki Yamanashi1,2,3 (1. Yokohama National University (Japan), 2. Institute of Advanced Sciences Yokohama National University (Japan), 3. Institute for Multidisciplinary Sciences Yokohama National University (Japan))
Keywords:
SFQ circuit,FPGA
Field programmable gate arrays (FPGAs) provide advantages in development time and cost compared to application-specific LSIs, as circuits can be programmed by the user even after fabrication. The island-style FPGA architecture consists of Logic Blocks (LBs), which perform calculation, Switch Blocks (SBs) and Connection Blocks (CBs), which determine routing directions. Although FPGAs based on single flux quantum (SFQ) circuits—characterized by low power consumption and high-speed operation—have been studied, a significant limitation has been their large area requirements. This constraint prevents sufficient enhancement of the density of look-up tables (LUTs) that implement logical operations within the LBs.In this study, we achieved miniaturization of a superconductor FPGA by employing logic gates that utilize external current for operation and reconfiguration, thereby enabling an increase in density of LUTs. We designed a superconductor FPGA using the AIST 10 kA/cm^2 Nb Advanced Process 2 (ADP2).
To reduce the area of the LB, we redesigned the decoder portion of the LUT from a Non-Destructive Read-Out flip-flop with Complementary Outputs (NDROC) in ADP2 cell library to an NDROC based on local magnetic flux bias (LFB). LFB is a technique that achieves phase shifting by coupling an external current into an inductance outside a superconducting loop, thereby inducing magnetic flux within the loop. For the memory cells, we employed Non-Destructive Read-Out flip-flops (NDROs) which can be reconfigured by external current. Compared with a decoder composed solely of NDROCs from the ADP2 cell library, the proposed design reduced power consumption by 44% and area by 22%.For interconnect structures, we focused on area reduction of SBs, which determine horizontal and vertical signal propagation paths. To this end, we designed NDROC which can be reconfigured by external current. Whereas a previous study required two splitters and three memory cells per input, our approach achieved area reduction by realizing the function with only two NDROCex. Compared with the previous work, power consumption and area were reduced by 55% and 57%, respectively. In the presentation, we will report on the measurement results of the fabricated chip.
To reduce the area of the LB, we redesigned the decoder portion of the LUT from a Non-Destructive Read-Out flip-flop with Complementary Outputs (NDROC) in ADP2 cell library to an NDROC based on local magnetic flux bias (LFB). LFB is a technique that achieves phase shifting by coupling an external current into an inductance outside a superconducting loop, thereby inducing magnetic flux within the loop. For the memory cells, we employed Non-Destructive Read-Out flip-flops (NDROs) which can be reconfigured by external current. Compared with a decoder composed solely of NDROCs from the ADP2 cell library, the proposed design reduced power consumption by 44% and area by 22%.For interconnect structures, we focused on area reduction of SBs, which determine horizontal and vertical signal propagation paths. To this end, we designed NDROC which can be reconfigured by external current. Whereas a previous study required two splitters and three memory cells per input, our approach achieved area reduction by realizing the function with only two NDROCex. Compared with the previous work, power consumption and area were reduced by 55% and 57%, respectively. In the presentation, we will report on the measurement results of the fabricated chip.