Presentation Information
[EDP2-02]Reduction of Logic Stages and Gate Count in RSFQ Circuits Synthesized with a Complete Set of Clockless Gates
*Nobutaka Kito1 (1. Chukyo University (Japan))
Keywords:
RSFQ Circuits,Clockless Gates,Technology Mapping,Logic Synthesis
Demand for high-performance computers continues to grow. Their power consumption is a major issue. Rapid single flux quantum (RSFQ) circuits are attracting attention as a device technology for low-power and high-performance computing systems. Each ordinary logic gate of RSFQ circuits has a clock input terminal and functions as a memory element. In RSFQ logic circuits, the number of clocked gates on any path from the circuit inputs to the logic gate must match. Insertions of D flip-flops are necessary to adjust the number of logic stages for unmatched paths, known as path-balancing. In circuits with large logic stages, the insertion of D flip-flops for path balancing and clock routing significantly impacts the area.
Therefore, designs of logic gates that have no clock terminal and output results triggered by data pulses, referred to as clockless gates in this study, have been investigated. It is not possible to realize a clockless NOT gate, but clockless designs have been proposed for other logic gates. A confluence buffer, which merges pulses fed to its inputs into its output, is used as a clockless OR gate [1]. Several designs of clockless AND and NIMPLY gates have been proposed [1]-[2]. Recently, a clockless XOR gate has also been proposed [3]. However, the benefits of utilizing a complete set of clockless gates, including clockless XOR, have not been investigated. In other words, it is unclear whether effectiveness is limited or saturated due to the absence of clockless NOTs.
This study clarifies the influence of available clockless gates on generated circuits during logic synthesis. This study examines generation of gate-level circuits from HDL descriptions in four conditions: 1) only clocked gates are available, 2) clockless OR is available in addition to ordinary clocked gates, 3) clockless AND and NIMPLY are available in addition to clockless OR, and 4) clockless EXOR is available in addition to clockless OR, AND, and NIMPLY gates. The last condition considers where ordinary RSFQ logic gates, except NOT, have their corresponding clockless ones. Previous work [4][5] did not consider conditions 2) and 4). This study uses a logic synthesis tool including a technology mapper developed to handle clockless gates [4][5]. It incorporates the designed supergate libraries necessary for mapping in those four conditions. The tool uses at most two clockless gates on paths between adjacent clocked gates to prevent dropping clock frequency and reduces the number of logic stages of circuits, i.e., the number of clocked gates between circuit inputs and outputs.
Combinational circuits in ISCAS85 benchmark circuits were synthesized for each of four conditions. The number of logic stages and gate count, including path-balancing DFFs, were evaluated. The evaluation results showed that the number of logic stages and gate count reduced as the number of available clockless gates increased, but that the number of logic stages was larger than the expected minimum values, i.e., one third of logic stages in circuits without clockless gates.
Therefore, designs of logic gates that have no clock terminal and output results triggered by data pulses, referred to as clockless gates in this study, have been investigated. It is not possible to realize a clockless NOT gate, but clockless designs have been proposed for other logic gates. A confluence buffer, which merges pulses fed to its inputs into its output, is used as a clockless OR gate [1]. Several designs of clockless AND and NIMPLY gates have been proposed [1]-[2]. Recently, a clockless XOR gate has also been proposed [3]. However, the benefits of utilizing a complete set of clockless gates, including clockless XOR, have not been investigated. In other words, it is unclear whether effectiveness is limited or saturated due to the absence of clockless NOTs.
This study clarifies the influence of available clockless gates on generated circuits during logic synthesis. This study examines generation of gate-level circuits from HDL descriptions in four conditions: 1) only clocked gates are available, 2) clockless OR is available in addition to ordinary clocked gates, 3) clockless AND and NIMPLY are available in addition to clockless OR, and 4) clockless EXOR is available in addition to clockless OR, AND, and NIMPLY gates. The last condition considers where ordinary RSFQ logic gates, except NOT, have their corresponding clockless ones. Previous work [4][5] did not consider conditions 2) and 4). This study uses a logic synthesis tool including a technology mapper developed to handle clockless gates [4][5]. It incorporates the designed supergate libraries necessary for mapping in those four conditions. The tool uses at most two clockless gates on paths between adjacent clocked gates to prevent dropping clock frequency and reduces the number of logic stages of circuits, i.e., the number of clocked gates between circuit inputs and outputs.
Combinational circuits in ISCAS85 benchmark circuits were synthesized for each of four conditions. The number of logic stages and gate count, including path-balancing DFFs, were evaluated. The evaluation results showed that the number of logic stages and gate count reduced as the number of available clockless gates increased, but that the number of logic stages was larger than the expected minimum values, i.e., one third of logic stages in circuits without clockless gates.