[EDP2] Digital, Quantum Information Technology, Materials and Fabrication

[EDP2-05] Demonstration of Stochastic Number Generator using Complementary Output Superconductive Random Number Generators

*Ryota Fukuzaki¹, Masaki Nagayama¹, Nobuyuki Yoshikawa^1,2,3, Yuki Yamanashi^1,2,3 (1. Yokohama National Univ. (Japan), 2. Yokohama National Univ. IAS (Japan), 3. Yokohama National Univ. IMS (Japan))

Keywords:

SFQ,Stochastic Computing

Stochastic computing (SC), a type of probabilistic computation, represents numerical values based on the probability of the presence of “1” in a binary sequence. These numerical values are called stochastic number (SN). One advantage of SC is that arithmetic operations such as addition and multiplication can be performed using only a small number of logic gates. Therefore, it is expected to be applied in fields such as wireless signal processing and neural networks, which make frequent use of multiplication and addition. When designing stochastic arithmetic circuits, the most significant bottleneck is a stochastic number generator (SNG), which converts binary numbers into stochastic numbers. Currently, the most commonly used SNG is the comparator type, but this method requires a large number of logic gates, contributing to an increase in circuit area. Therefore, we focused on the random number generator in a single flux quantum circuit, superconductive random number generators (SRNGs) . SRNGs are a true random number generator that utilizes physical random numbers such as thermal noise, offering advantages such as high speed, small area, and low power consumption. In this study, we branched the output of the SRNG into a DFF and a NOT gate, and by using multiple SRNGs with complementary outputs (RNGCs), we conducted a new SNG design and operational demonstration. We designed the SNG using the AIST 10 kA/cm^2 Nb high-speed standard process. The operating principle of the circuit will be explained using the designed 4-bit SNG as an example. When outputting SN, the SN value is represented in binary and input into four Non-Destructive Read-out flip-flops (NDROs). For example, an SN value of 9/16 is represented in binary as 1001, so inputs are fed into the bottom and top NDRO. Here, when clock pulses are input into the bottom RNGC, the four RNGCs output pulses from one of the lower outputs with probabilities of 1/2, 1/4, 1/8, and 1/16, respectively. In NDRO, no output is generated even if clock pulses are input unless there is an input, so taking the logical OR of these results in the SN value of 9/16. In NDROs, the state is not reset even when clock pulses are input, so even when multiple bits of SN are required, SN can be obtained by simply inputting the same number of clock pulses. To change the SN value, first reset each NDROs, then input the binary number corresponding to the desired SN. In this way, SNG can be created using RNGCs. Compared to the SNG using a digital comparator, the proposed circuit reduces the number of logic gates used. When comparing the actual 4-bit SNG created, the number of Josephson junctions was reduced by approximately 27% compared to the SNG using a digital comparator.