[EDP2] Digital, Quantum Information Technology, Materials and Fabrication

[EDP2-06] Design of Asynchronous Single Flux Quantum OR Gate with Input-Pattern-Independent Output Delay

*Taisei Yahata¹, Nobuyuki Yoshikawa^1,2,3, Yuki Yamanashi^1,2,3 (1. Yokohama National University (Japan), 2. Institute of Advanced Sciences, Yokohama National University (Japan), 3. Institute of Multidisciplinary Sciences, Yokohama National University (Japan))

Keywords:

Single flux quantum circuit,Asynchronous design,Self-clocking method,Logic gate

Single flux quantum (SFQ) circuits provide high-speed operation and low power consumption, attracting attention as a promising integrated circuit technology. Since all SFQ logic gates require clock signals for operation, large-scale SFQ circuits face challenges such as increased timing adjustment complexity and larger circuit area. To resolve these problems, asynchronous SFQ circuit designs using logic gates that operate without clock signals have been proposed. A self-clocking method is one of the asynchronous SFQ circuit design methodologies [1]. Figure 1 (a) shows a block diagram of an asynchronous logic gate using the self-clocking method. The logic gate achieves asynchronous operation by branching the inputs to a synchronous logic gate and using them as a clock input. This method enables the implementation of basic logic gates, including exclusive OR (XOR) gates, with a small circuit area. However, the output delay of self-clocking OR gates varies significantly depending on input patterns due to asymmetric inputs. This characteristic makes asynchronous SFQ circuit design difficult. Therefore, asynchronous SFQ logic gates with output delay characteristics independent of input patterns are required. In this study, we propose an asynchronous OR gate with output delay characteristics independent of input patterns using the self-clocking method. Figure 1 (b) shows a block diagram of the proposed OR gate. The issue occurs because the time required to generate a clock signal differs between the input patterns (A, B) = (0, 1) or (1, 0) and (A, B) = (1, 1) due to the difference in the number of SFQ pulses input to the merger. The OR logic can be expressed as the logical sum of XOR and AND operations, i.e., A + B = (A ⊕ B) + (A · B). By constructing the OR gate from XOR and AND gates, input asymmetry is eliminated. The XOR gate operates for (A, B) = (0, 1) or (1, 0), while the AND gate operates for (A, B) = (1, 1), thus achieving output delay characteristics independent of input patterns. We designed the proposed OR gate using the AIST 10 kA/cm² Nb high-speed process [2]. In analog circuit simulations, we confirmed that there was no difference in output delay depending on input patterns at the standard bias voltage. The proposed OR gate consumed 4.28 times more static power than the conventional self-clocking OR gate due to its more complex structure. To further evaluate asynchronous OR gates, we designed asynchronous OR gates with 2^N inputs and confirmed the correct operation even for N = 4, which did not function in conventional self-clocking OR gates. At an input frequency of 10 GHz, the bias voltage margin was 76.4%–124.4% for N = 1 and 84.0%–117.6% for N = 4, indicating that the reduction in bias voltage margin with increasing N is small.The proposed OR gate in this study achieves output delay characteristics independent of input patterns, enabling asynchronous SFQ circuit design with a large number of logic stages without concern for input patterns.