[20p-A308-1~20] CS.2 Code-sharing Session of 3.2 & 4.4

6:45 PM - 7:00 PM JST(9:45 AM - 10:00 AM UTC)Presentation by Applicant for JSAP Young Scientists Presentation Award

[20p-A308-20] Rapidly convergent unitary processor using few-layer-redundant multi-plane light conversion

〇Yoshitaka Taguchi¹, Yunzhuo Wang², Ryota Tanomura¹, Takuo Tanemura¹, Yasuyuki Ozeki¹ (1.Univ. Tokyo, 2.Preferred Networks Inc.)

Keywords:

multi-plane light conversion,unitary converter,matrix optimization

Among programmable optical unitary converters, those using multi-plane light conversion (MPLC) are known to have extremely high tolerance to fabrication errors. However, no fast configuration method for realizing the desired unitary transformations has been discovered due to the complex mathematical structure of MPLC. In this study, we present a fast-configurable unitary converter using MPLC.